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? semiconductor components industries, llc, 2001 june, 2001 rev. 0 1 publication order number: mc100ep16vc/d mc100ep16vc 3.3v / 5vecl differential receiver/driver with high gain and enable output the ep16vc is a worldclass differential receiver/driver. the device is functionally equivalent to the ep16 and lvep16 devices but with high gain and enable output. the ep16vc provides an en input which is synchronized with the data input (d) signal in a way that provides glitchless gating of the qhg and qhg outputs. when the en signal is low, the input is passed to the outputs and the data output equals the data input. when the data input is high and en goes high, it will force the q hg low and the q hg high on the next negative transition of the data input. if the data input is low when the en goes high, the next data transition to a high is ignored and q hg remains low and q hg remains high. the next positive transition of the data input is not passed on to the data outputs under these conditions. the q hg and q hg outputs remain in their disabled state as long as the en input is held high. the en input has no influence on the q output and the data input is passed on (inverted) to this output whether en is high or low. this configuration is ideal for crystal oscillator applications where the oscillator can be free running and gated on and off synchronously without adding extra counts to the output. the v bb pin, an internally generated voltage supply, is available to this device only. for single-ended input conditions, the unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb should be left open. the 100 series contains temperature compensation. ? 310 ps typical prop delay q , 380 ps typical prop delay qhg, qhg ? gain > 200 ? maximum frequency > 3 ghz typical ? pecl mode operating range: v cc = 3.0 v to 5.5 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = 3.0 v to 5.5 v ? open input default state ? q hg output will default low with d inputs open or at v ee ? v bb output this document contains information on a product under development. on semiconductor reserves the right to change or discontinue this product without notice. http://onsemi.com device package shipping ordering information mc100ep16vcd so8 98 units/rail mc100ep16vcdr2 so8 2500 tape & reel mc100ep16vcdt tssop8 100 units/rail mc100ep16vcdtr2 tssop8 2500 tape & reel *for additional information, see application note and8002/d k = mc100 a = assembly location l = wafer lot y = year w = work week so8 d suffix case 751 marking diagrams* tssop8 dt suffix case 948r alyw kep66 1 8 1 8 1 8 kp66 1 8 alyw
mc100ep16vc http://onsemi.com 2 figure 1. 8lead pinout (top view) and logic diagram pin function pin description d* ecl data input q ecl data output q hg , q hg ecl high gain data outputs en * ecl enable input v bb reference voltage output v cc positive supply v ee negative supply 1 2 3 45 6 7 8 q hg v ee v cc d q hg en v bb q v bb d len q latch oe * pins will default low when left open. attributes characteristics value internal input pulldown resistor 75 k internal input pullup resistor n/a esd protection human body model machine model charged device model > 4 kv > 200 v > 2 kv moisture sensitivity, indefinite time out of drypack (note 1) level 1 flammability rating oxygen index ul94 code v0 a 1/8o 28 to 34 transistor count 167 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. maximum ratings (note 2) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 6 v v ee necl mode power supply v cc = 0 v 6 v v i pecl mode input voltage v ee = 0 v v i v cc 6 v v i pecl mode in ut voltage necl mode input voltage v ee 0 v v cc = 0 v v i v cc v i v ee 6 6 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma ta operating temperature range 40 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 8 soic 8 soic 190 130 c/w c/w q jc thermal resistance (junction to case) std bd 8 soic 41 to 44 c/w q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 8 tssop 8 tssop 185 140 c/w c/w q jc thermal resistance (junction to case) std bd 8 tssop 41 to 44 c/w t sol wave solder <2 to 3 sec @ 248 c 265 c 2. maximum ratings are those values beyond which device damage may occur.
mc100ep16vc http://onsemi.com 3 100ep dc characteristics, pecl v cc = 3.3 v, v ee = 0 v (note 3) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 25 36 45 30 40 50 32 42 52 ma v oh output high voltage (note 4) 2105 2230 2355 2105 2230 2355 2105 2230 2355 mv v ol output low voltage (note 4) 1305 1430 1555 1305 1430 1555 1305 1430 1555 mv v ih input high voltage (single ended) 2075 2420 2075 2420 2075 2420 mv v il input low voltage (single ended) 1355 1675 1355 1675 1355 1675 mv v bb output voltage reference 1725 1825 1925 1700 1800 1900 1675 1775 1875 mv v ihcmr input high voltage common mode range (differential) (note 5) 2.0 3.3 2.0 3.3 2.0 3.3 v i ih input high current 150 150 150 m a i il input low current d en 0.5 150 0.5 150 0.5 150 m a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. input and output parameters vary 1:1 with v cc . v ee can vary +0.3 v to 2.2 v. 4. all loading with 50 ohms to v cc 2.0 volts. 5. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 100ep dc characteristics, pecl v cc = 5.0 v, v ee = 0 v (note 6) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 25 36 45 30 40 50 32 42 52 ma v oh output high voltage (note 7) 3805 3930 4055 3805 3930 4055 3805 3930 4055 mv v ol output low voltage (note 7) 3005 3130 3255 3005 3130 3255 3005 3130 3255 mv v ih input high voltage (single ended) 3775 4120 3775 4120 3775 4120 mv v il input low voltage (single ended) 3055 3375 3055 3375 3055 3375 mv v bb output voltage reference 3425 3525 3625 3400 3500 3600 3375 3475 3575 mv v ihcmr input high voltage common mode range (differential) (note 8) 2.0 5.0 2.0 5.0 2.0 5.0 v i ih input high current 150 150 150 m a i il input low current d en 0.5 150 0.5 150 0.5 150 m a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. input and output parameters vary 1:1 with v cc . v ee can vary +2.0 v to 0.5 v. 7. all loading with 50 ohms to v cc 2.0 volts. 8. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 100ep dc characteristics, necl v cc = 0 v; v ee = 5.5 v to 3.0 v (note 9) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 25 36 45 30 40 50 32 42 52 ma v oh output high voltage (note 10) 1195 1070 945 1195 1070 945 1195 1070 945 mv v ol output low voltage (note 10) 1995 1870 1745 1995 1870 1745 1995 1870 1745 mv v ih input high voltage (single ended) 1225 880 1225 880 1225 880 mv v il input low voltage (single ended) 1945 1625 1945 1625 1945 1625 mv v bb output voltage reference 1575 1475 1375 1600 1500 1400 1625 1525 1425 mv v ihcmr input high voltage common mode range (differential) (note 11) v ee +2.0 0.0 v ee +2.0 0.0 v ee +2.0 0.0 v i ih input high current 150 150 150 m a i il input low current d en 0.5 150 0.5 150 0.5 150 m a note: ep circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been establi shed. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. input and output parameters vary 1:1 with v cc . 10. all loading with 50 ohms to v cc 2.0 volts. 11. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc100ep16vc http://onsemi.com 4 ac characteristics v cc = 0 v; v ee = 3.0 v to 5.5 v or v cc = 3.0 v to 5.5 v; v ee = 0 v (note 12) 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum frequency (see figure 2. f max /jitter) > 3 > 3 > 3 ghz t plh , t phl propagation delay (differential) q (differential) qhg, qhg (single ended) q (single ended) qhg, qhg 200 250 250 300 280 360 330 410 350 450 400 500 250 300 300 350 310 380 360 430 400 500 450 550 275 325 325 375 340 430 390 480 425 525 475 575 ps t s setup time en = l to d en =h to d 50 100 15 60 50 100 5 40 50 100 18 10 ps t h hold time en = l to d en =h to d 100 50 50 15 100 50 40 20 100 50 5 20 ps t skew duty cycle skew (note 13) 5.0 20 5.0 20 5.0 20 ps t jitter cycletocycle jitter (see figure 2. f max /jitter) 0.2 < 1 0.2 < 1 0.2 < 1 ps v pp input voltage swing (differential) hg (differential) q 25 150 800 800 1200 1200 25 150 800 800 1200 1200 25 150 800 800 1200 1200 mv t r t f output rise/fall times q (20% 80%) qhg, qhg 200 70 300 130 400 220 250 80 350 150 450 240 250 100 350 170 500 270 ps 12. measured using a 750 mv source, 50% duty cycle clock source. all loading with 50 ohms to v cc 2.0 v. 13. skew is measured between outputs under identical transitions. duty cycle skew is defined only for differential operation whe n the delays are measured from the cross point of the inputs to the cross point of the outputs.
mc100ep16vc http://onsemi.com 5 single ended input 0 100 200 300 400 500 600 700 800 900 0 500 1000 1500 2000 2500 3000 3500 4000 figure 2. f max /jitter for qhg, qhg output frequency (mhz) 1 2 3 4 5 6 7 8 v outpp (mv) jitter out ps (rms) 9 0 100 200 300 400 500 600 700 800 900 0 500 1000 1500 2000 2500 3000 3500 4000 figure 3. f max /jitter for q output frequency (mhz) 1 2 3 4 5 6 7 8 v outpp (mv) jitter out ps (rms) 9
mc100ep16vc http://onsemi.com 6 differential inputs 0 100 200 300 400 500 600 700 800 900 0 500 1000 1500 2000 2500 3000 figure 4. f max /jitter for qhg, qhg output frequency (mhz) 1 2 3 4 5 6 7 8 v outpp (mv) jitter out ps (rms) 9 0 100 200 300 400 500 600 700 800 900 0 500 1000 1500 2000 2500 3000 figure 5. f max /jitter for q output frequency (mhz) 1 2 3 4 5 6 7 8 v outpp (mv) jitter out ps (rms) 9
mc100ep16vc http://onsemi.com 7 v tt = v cc 2.0 v figure 6. typical termination for output driver and device evaluation (refer to application note and8020 termination of ecl logic devices.) driver device receiver device q qb d db 50 50 v tt resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1504 metastability and the eclinps family an1568 interfacing between lvds and ecl an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8009 eclinps plus spice i/o model kit and8020 termination of ecl logic devices for an updated list of application notes, please see our website at http://onsemi.com.
mc100ep16vc http://onsemi.com 8 package dimensions so8 d suffix plastic soic package case 75107 issue w seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 x y g m y m 0.25 (0.010) z y m 0.25 (0.010) z s x s m
mc100ep16vc http://onsemi.com 9 package dimensions dim min max min max inches millimeters a 2.90 3.10 0.114 0.122 b 2.90 3.10 0.114 0.122 c 0.80 1.10 0.031 0.043 d 0.05 0.15 0.002 0.006 f 0.40 0.70 0.016 0.028 g 0.65 bsc 0.026 bsc l 4.90 bsc 0.193 bsc m 0 6 0 6 seating plane pin 1 1 4 85 detail e b c d a g detail e f m l 2x l/2 u s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) t v w 0.25 (0.010) 8x ref k ident k 0.25 0.40 0.010 0.016 tssop8 dt suffix plastic tssop package case 948r02 issue a notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. terminal numbers are shown for reference only. 6. dimension a and b are to be determined at datum plane -w-.
mc100ep16vc http://onsemi.com 10 notes
mc100ep16vc http://onsemi.com 11 notes
mc100ep16vc http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc100ep16vc/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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